This invention relates in general to the field of phase detectors and more specifically to a sample and hold phase detector with low spurious performance and method.
The design of sample and hold phase detectors for high-performance frequency synthesizers is a key for low spurious (reference feedthrough) frequency synthesizer designs. In FIG. 1 there is shown a typical phase lock loop (PLL) 100 using a SH phase detector 102. If the SH phase detector 102 is not perfect then spurs will show up in the output signal (fout) 104. The offset frequencies of these spurs are multiples of the reference frequency (FR) 106.
A simplified electrical model schematic of a prior art SH phase detector 200 using the PLL of FIG. 1 is shown in FIG. 2. While in FIG. 3, the waveforms for VR, VSH and VPR are shown. The VR signal is the ramp control voltage, the VSH signal is the sample and hold pulse, and the VPR signal is the pre-charge signal. It should be noted that the conventional digital block, which generates these signals, is not shown in FIG. 2. SH phase detector 200 includes a ramp current generator 204, a ramp capacitor, CR206, a sample and hold switch 208, a sample and hold capacitor, CSH210 and buffer 212.
If the SH phase detector 200 is implemented in complimentary metal-oxide semiconductor (CMOS) using a deep sub-micron CMOS process as an example, the SH phase detector 200 will leak a current during the hold period. Line 302 in FIG. 3 shows an ideal constant voltage level at node N 202 while the SH phase detector 200 is in the hold or locked condition. However, line 304 shows the actual voltage level at node N 202 due to leakage current. This leakage current causes a voltage drift which causes unwanted spurs to be generated by the synthesizer that uses the SH phase detector 200. The leakage current can be large, typically in the order of one nano-amp if the SH switch 208 has low threshold voltage (VT) devices operating at high temperature.
In FIG. 4, there is shown a typical prior art CMOS switch implementation. For the example shown in FIG. 4, the leakage current (ILeak) will happen during the phase detector hold period 306. The PMOS device 402 has a VGS=0 and an |VDS|=VCCxe2x88x92VN.
Since a typical prior art SH phase detector has a typically long hold period, for example, for a 200 KHz compare frequency [R, V signals], thold is approximately 5 microseconds using a capacitor (CSH)=5 pF. The xcex94V 308 due to leakage is equal to: xcex94V=[I/C]xc3x97[t]=(1 nA/5 pF)xc3x97(5 uS)=1 millivolt. This xcex94V during lock can cause spurs at fout+/xe2x88x92200 kHz as large as xe2x88x9220 dBc (without the filter attenuation). The NMOS device 402 shown in FIG. 4 will not suffer because it""s VGS is xe2x88x92VN and the leakage current is too low. The leakage current 404 problem can be much more sever than other issues associated with SH phase detectors including clock feedthrough and charge injection due to the CMOS switch.
Conventional sample and hold (SH) phase detectors used in frequency synthesizers sometimes also suffer from voltage glitches during lock. One reason for this problem is the leakage current of the sampling switch which results in charge leakage in the holding capacitor. A need exists in the art for method of reducing the leakage current in a SH phase detector and hence improves the reference feedthrough issue in the frequency synthesizer using the SH phase detector.